The present invention generally relates to a logic circuit using a transistor having a negative differential conductance, and more particularly to a three-input exclusive-OR or exclusive-NOR circuit using a transistor having a negative differential conductance.
As is well known, an exclusive-OR circuit is used for configuring an adder circuit. A two-input exclusive-OR circuit generates a low-level output signal when both the two input signals have an identical level, and generates a high-level output signal when both the two input signals have different levels. There is also known a three-input exclusive-OR circuit, which generates a low-level output signal when an even number of input signals (including zero) which are at a high level is applied thereto, and generates a high-level output signal when an odd number of input signals which are at the high level is applied thereto. The output signal of such a three-input exclusive-OR circuit corresponds to the result of an addition (sum) operation on binary values including a carry bit. Thus, a three-input exclusive-OR circuit is used for configuring a full adder.
The operation of the three-input exclusive-0R circuit is written as follows: ##EQU1## where A, B and C are respectively the input signals to the three-input exclusive-OR circuit, and Q is the output signal thereof. The three-input exclusive-0R circuit can be configured by a combination of gates realizing the equation (1).
FIG. 1 is a circuit diagram of a conventional three-input exclusive-OR circuit which employs emitter-coupled logic (ECL) circuits (see M. Suzuki et al., "GATE ARRAYS", 1988 IEEE International Solid-State Circuits Conference, ISSCC 88, Wednesday, Feb. 17, 1988, pp. 70-71). In FIG. 1, S indicates the sum of the three inputs including the carry bit, and A, B, C and S are the inverted versions of A, B, C and S, respectively.
However, the configuration shown in FIG. 1 needs a large number of transistors, and cannot realize a high integration density.
On the other hand, there is known a two-input exclusive-NOR circuit using a transistor having a negative differential conductance (see N. Yokoyama et al., "A NEW FUNCTIONAL, RESONANT-TUNNELING HOT ELECTRON TRANSISTOR (RHET)", Japanese Journal of Applied Physics, Vol. 24, No. 11, November, 1985, pp. L853-L854).
FIG. 2 is a circuit diagram of a two-input exclusive-NOR circuit proposed in the above-mentioned document. A transistor Tr is formed of an RHET. The input signal A is applied to the base of the transistor Tr via a resistor R1, and the input signal B is applied to the base of the transistor Tr via a resistor R2. The emitter of the transistor Tr is directly grounded. The collector of the transistor Tr is coupled to a power source via a resistor R3. The output signal Q of the two-input exclusive-NOR circuit is obtained at the collector of the transistor.
However, in order to realize the three-input exclusive-NOR circuit, it is necessary to use two two-input exclusive-NOR circuits connected in series. The use of such a two-input exclusive-NOR circuit needs a reduced number of transistors necessary to realize the three-input exclusive-NOR circuit.